Published Papers
SNUG 06: SystemVerilog Assertions are for Design Engineers Too!
SNUG 04: Being Assertive With Your X (SystemVerilog Assertions for Dummies)
SNUG 03: Synchronous Resets & Asynchronous Resets Design Techniques--Part Deux
SNUG 03: HDVL += (HDL & HVL) SystemVerilog 3.1 - The Hardware Description AND Verification Language
SNUG 02: Synchronous Resets? Asynchronous Resets? I Am So Confused! How Will I Ever Know Which to Use?
SNUG 01: Getting the Most Out of the New Verilog-2000 Standard
SNUG 00: Habits of Deficient ASIC Design
SNUG 99: RTL Coding Styles That Yield Simulation and Synthesis Mismatches
SNUG 97: Synthesis of a Million-Gate ASIC