LCDM ENGINEERING

Independent consulting,  contracting,  and teaching ASIC design methodology and hardware

As an Independent Consultant, Mr. Mills has taught over one hundred Verilog and SystemVerilog training courses and also some VHDL training courses.

In addition to training, Mr. Mills has taken on contract jobs for a number of companies including Intel, Evans & Sutherland, Sonic Wall, L3 Communications, and Utah Scientific.

Instigator and lead of division ASIC Technology Working Group,  which maintains current ASIC/FPGA processes and coordinates EDA tools and training used for these processes

Assisted in resolving backend issues for a numbers of ASICs,  including updating vanishing vendor ASICs and supporting tool flow for new ASICs

Lead Engineer for processing a million-gate ASIC

Developed and presented a internal 40-hour VHDL training course

Established the method for ASIC development using current technology such as VHDL,  Synopsys,  DFT and scan approaches for the division

Sub-contract (15-20 hours/week).   Developed ASIC process for division using VHDL,  Synopsys,  and DFT/scan methodology

Participated in a team designing a next-generation modem ASIC

Assisted Motorola in Synopsys 3.0B synthesis for their Iridium project

Boeing 777 Project -  60,000-gate CMOS gate array (Bus Interface Unit),  running at 40 MHz

Updated Honeywell ASIC design process and trained new ASIC designers on the ASIC process and tools including VHDL,  Verilog,  Design for Test/Scan Methodology and Synopsys synthesis

Board design -  2 separate bus interfaces for Honeywell,  Satellite Systems Division

10,000-gate CMOS gate array,  mixed signal,  10V,  programmable sync generator for Mini-FLIR

2500-gate ECL gate array,  running at 274 MHz,  high speed multiplexer,  used for specialized data link communications

2500-gate ECL gate array,  running at 137 MHz,  high speed demultiplexer,  used for data link communications

6000-gate CMOS gate array,  running at 12.5 MHZ,  programmable multiplexer,  used for data link communications

"SystemVerilog Assertions Are For Design Engineers Too!" presented at the 2006 San Jose Synopsys Users Group Conference, published in the conference proceedings (voted 2nd Best Paper)

"Being Assertive With Your X (SystemVerilog Assertions for Dummies)" presented at the 2004 San Jose Synopsys Users Group Conference, published in the conference proceedings

"Synchronous Resets & Asynchronous Resets Design Techniques--Part Deux" presented at the 2003 Boston Synopsys Users Group Conference,  published in the conference proceedings

"HDVL += (HDL & HVL) SystemVerilog 3.1 - The Hardware Description AND Verification Language" presented at the 2003 San Jose and Europe Synopsys Users Group Conferences,  published in the individual conference proceedings

"Synchronous Resets? Asynchronous Resets? I Am So Confused!"  presented at the 2002 San Jose Synopsys Users Group Conference, published in the conference proceedings

"Getting the Most Out of the New Verilog-2000 Standard"  presented at the 2001 San Jose and Europe Synopsys Users Group Conferences, published in the individual conference proceedings

"Habits of Deficient ASIC Design"  presented at the 2000 San Jose Synopsys Users Group Conference,  published in the conference proceedings

"RTL Coding Styles that Yield Simulation and Synthesis Mismatches"  presented at the 1999 San Jose Synopsys Users Group Conference,  published in the conference proceedings

"Synthesis of a Million-Gate ASIC"  presented at the 1997 San Jose Synopsys Users Group Conference,  published in the conference proceedings

Member of IEEE Verilog and SystemVerilog Committees, 2003-pres.
Member of Technical Committee,  2003-pres. Europe, San Jose, and Boston Synopsys Users Group Conferences

Technical Chairman,  2003 Europe Synopsys Users Group Conference
Technical Chairman,  2002 Europe Synopsys Users Group Conference
Technical Chairman,  2001 Europe Synopsys Users Group Conference
Technical Chairman,  2000 San Jose Synopsys Users Group Conference
Technical Chairman,  1999 Boston Synopsys Users Group Conference
Technical Chairman,  1999 San Jose Synopsys Users Group Conference
Technical Chairman,  1998 San Jose Synopsys Users Group Conference>

Certified Instructor for Sunburst Design,  Inc.  (Beginning and Advanced Verilog, SystemVerilog)
Certified Instructor for Sutherland HDL,  Inc.  (Verilog and SystemVerilog)

Other references available upon request.