LCDM ENGINEERING

Certified in Verilog, SystemVerilog, and VHDL

Consultant providing training and support for debugging SystemVerilog code and SystemVerilog Assertions.

Training courses include SystemVerilog for Synthesis, SystemVerilog Verification and SystemVerilog Assertions.

Taught hundreds of training courses and several thousand engineers.

Current Vice Chair of IEEE 1800 Verilog and SystemVerilog Standards Committee.

Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them by Stuart Sutherland and Don Mills (Hardcover, June 2009)

"If Chained Implications in Properties Weren't So Hard, They'd be Easy (Tricky SVA Properties Made Easy)" presented at the 2009 San  Jose Synopsys Users Group Conference, published in the conference proceedings (voted 3rd Best Paper)

"Gotcha Again--More Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know" presented at the 2007 San  Jose Synopsys Users Group Conference, published in the conference proceedings (voted 2nd Best Paper and Honorable Mention Technical Committee Award)

"Standard Gotchas--Subtleties in the Verilog and SystemVerilog Standards that Every Engineer Should Know" presented at the 2006 Boston Synopsys Users Group Conference, published in the conference proceedings (voted Best Paper Technical Committee Award)

"SystemVerilog Assertions Are For Design Engineers Too!" presented at the 2006 San Jose Synopsys Users Group Conference, published in the conference proceedings (voted 2nd Best Paper)

"Being Assertive With Your X (SystemVerilog Assertions for Dummies)" presented at the 2004 San Jose Synopsys Users Group Conference, published in the conference proceedings

"Synchronous Resets & Asynchronous Resets Design Techniques--Part Deux" presented at the 2003 Boston Synopsys Users Group Conference,  published in the conference proceedings

"HDVL += (HDL & HVL) SystemVerilog 3.1 - The Hardware Description AND Verification Language" presented at the 2003 San Jose and Europe Synopsys Users Group Conferences,  published in the individual conference proceedings

"Synchronous Resets? Asynchronous Resets? I Am So Confused!"  presented at the 2002 San Jose Synopsys Users Group Conference, published in the conference proceedings

"Getting the Most Out of the New Verilog-2000 Standard"  presented at the 2001 San Jose and Europe Synopsys Users Group Conferences, published in the individual conference proceedings

"Habits of Deficient ASIC Design"  presented at the 2000 San Jose Synopsys Users Group Conference,  published in the conference proceedings

"RTL Coding Styles that Yield Simulation and Synthesis Mismatches"  presented at the 1999 San Jose Synopsys Users Group Conference,  published in the conference proceedings

"Synthesis of a Million-Gate ASIC"  presented at the 1997 San Jose Synopsys Users Group Conference,  published in the conference proceedings

Member of IEEE Verilog and SystemVerilog Committees, 2003-pres.
Member of Technical Committee,  2003-pres. Europe, San Jose, and Boston Synopsys Users Group Conferences

Technical Chairman,  2003 Europe Synopsys Users Group Conference
Technical Chairman,  2002 Europe Synopsys Users Group Conference
Technical Chairman,  2001 Europe Synopsys Users Group Conference
Technical Chairman,  2000 San Jose Synopsys Users Group Conference
Technical Chairman,  1999 Boston Synopsys Users Group Conference
Technical Chairman,  1999 San Jose Synopsys Users Group Conference
Technical Chairman,  1998 San Jose Synopsys Users Group Conference>

Certified Instructor for Sunburst Design,  Inc.  (Beginning and Advanced Verilog, SystemVerilog)
Certified Instructor for Sutherland HDL,  Inc.  (Verilog and SystemVerilog)