In-house consultant providing training and support for debugging SystemVerilog code and SystemVerilog Assertions.

Training courses include SystemVerilog for Synthesis, SystemVerilog Verification and SystemVerilog Assersions.

Headed the selection team for SystemVerilog verification methodology, deciding between OVM and VMM. Received training for both OVM and VMM. Provided support to design and verification teams during implementation of the selected methodology.

Develop methodology and guidelines for implementing UPF for designs.

Member of IEEE Verilog and SystemVerilog Committees.

Independent consulting,  contracting,  and teaching ASIC design methodology and hardware

As an Independent Consultant, Mr. Mills has taught over one hundred Verilog and SystemVerilog training courses and also some VHDL training courses.

In addition to training, Mr. Mills has taken on contract jobs for a number of companies including Intel, Evans & Sutherland, Sonic Wall, L3 Communications, and Utah Scientific.

(Same company, many names via acquisitions and mergers.)

Instigator and lead of division ASIC Technology Working Group,  which maintains current ASIC/FPGA processes and coordinates EDA tools and training used for these processes

Assisted in resolving backend issues for a numbers of ASICs,  including updating vanishing vendor ASICs and supporting tool flow for new ASICs

Lead Engineer for processing a million-gate ASIC

Developed and presented a internal 40-hour VHDL training course

Established the method for ASIC development using current technology such as VHDL,  Synopsys,  DFT and scan approaches for the division

Sub-contract (15-20 hours/week).   Developed ASIC process for division using VHDL,  Synopsys,  and DFT/scan methodology

Participated in a team designing a next-generation modem ASIC

Assisted Motorola in Synopsys 3.0B synthesis for their Iridium project

Boeing 777 Project -  60,000-gate CMOS gate array (Bus Interface Unit),  running at 40 MHz

Updated Honeywell ASIC design process and trained new ASIC designers on the ASIC process and tools including VHDL,  Verilog,  Design for Test/Scan Methodology and Synopsys synthesis

Board design -  2 separate bus interfaces for Honeywell,  Satellite Systems Division

10,000-gate CMOS gate array,  mixed signal,  10V,  programmable sync generator for Mini-FLIR

2500-gate ECL gate array,  running at 274 MHz,  high speed multiplexer,  used for specialized data link communications

2500-gate ECL gate array,  running at 137 MHz,  high speed demultiplexer,  used for data link communications

6000-gate CMOS gate array,  running at 12.5 MHZ,  programmable multiplexer,  used for data link communications